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ASIC design services include:
ASIC Product Definition
Architectural definitions and specifications
Design ground rules generation
Technology evaluation/Vendor selection
Logical Partitioning
ASIC Design
RTL code generation
(Verilog, System Verilog, and VHDL)
High-speed interface design
Multiple clock domain design
Logic synthesis
ASIC Verification
Testbench generation
Functional simulation
Formal verification
Code coverage analysis
High-level modeling
Equivalency checking
Constrained random testing
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FPGA design services include:
FPGA Product Definition
Architectural definitions and specifications
Design ground rules generation
Technology evaluation/Vendor selection
IP block selection
FPGA Design
RTL code generation (VHDL, Verilog)
High-speed interface design
Multiple clock domain design
Logic synthesis
Vendor fuctional macros
IP block integration
FPGA Verification
Testbench generation
Functional simulation
Post-Synthesis simulation
Constrained random verification
Assertions
FPGA Compilation and Analysis
Partitioning
Clock optimization
Design translation
Synthesis optimization
I/O planning and analysis
Static timing analysis
Design closure
FPGA Design Delivery
RTL design source files
Simulation test bench
Suite of verification tests
Implementation specification
Verification plan and checklist
CAD tools, scripts, and log files |
